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W971GG6JB
11.10 Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CLK
CMD
Post CAS
READ A
NOP
Post CAS
READ B
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQS
AL = 2
RL = 5
CL = 3
DQ's
DOUT
A0
DOUT
A1
DOUT
A2
DOUT
A3
DOUT
B0
DOUT
B1
DOUT
B2
Note:
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and
every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are
activated.
11.11 Seamless burst write operation: RL = 5 ( WL = 4, BL = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CLK
CMD
Post CAS
Write A
NOP
Post CAS
Write B
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQS
WL = RL - 1 = 4
DQ's
DIN
A0
DIN
A1
DIN
A2
DIN
A3
DIN
B0
DIN
B1
DIN
B2
DIN
B3
Note:
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four
clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Publication Release Date: Sep. 24, 2013
- 74 -
Revision A09
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